Solid state imagers have been constructed for enabling image acquisition. A solid state imager typically consists of an array of photosensitive pixels. Each pixel site must have a mechanism that converts the photon flux incident on that site into an electrical signal, i.e., a current source proportional to the incident photon flux, a storage site on which to store the collected signal between readouts, and a switch which provides a low impedance readout path when the pixel is interrogated, and provide isolation when the pixel is not interrogated. Each of the photosensitive pixels typically comprises one or more solid state elements, such as diodes or transistors. During operation, the array of pixels of the solid state imager is exposed to an incident light and each of the pixels generates an output signal proportional to the incident photon flux it receives. The solid state imager can thus enable image acquisition by addressing each of the pixels in the array and determining the magnitude of the signal from each of the pixels. FIG. 1 illustrates the structure of a typical prior art solid state imager 10.
Referring to FIG. 1, solid state imager 10 includes a photosensitive pixel array 11 coupled to a horizontal scanning circuit 13 via a plurality of column lines 17a through 17n, and to a vertical scanning circuit 14 via a plurality of row lines 16a through 16n. Vertical scanning circuit 14 and horizontal scanning circuit 13 are coupled to output circuit 15. Photosensitive pixel array 11 includes a plurality of pixels, each comprises a photodiode and a switching diode connected in opposite directions to one of row lines 16a-16n and one of column lines 17a-17n, respectively. Horizontal and vertical scanning circuits 13 and 14 are composed of shift registers and transistor switches. To read out the light signal from each of the pixels in array 11, row and column lines 16a-16n and 17a-17n are connected successively to output circuit 15 by scanning circuits 13 and 14, and the pulse required in reading out the light signal from each pixel is applied to it by vertical scanning circuit 14.
As is known, a pixel which operates in a photon flux integration mode is typically required to possess three fundamental properties. First, the pixel must generate a current that is proportional to the incident photon flux. Secondly, the pixel must be able to integrate the photo generated current and temporarily store the accumulated charge. Finally, a switch is required which in its OFF condition isolates the PN junction of the pixel from other pixels and in its ON condition has a very low impedance to allow rapid and complete read out of the accumulated charge.
FIG. 2 illustrates in electrical schematic circuit form the structure of a prior art pixel 12 of array 11 of FIG. 1, which possesses the above described properties. Referring to FIG. 2, pixel 12 includes a photodiode 23 and a switching diode 22 connected together in opposite direction. Capacitors 24 and 25 are parasitic capacitors of diodes 22-23, respectively. During the readout time (i.e., a pulse time), pulse generator 21 applies a pulse having a voltage V.sub.O to the anode of diode 22 to forward bias diode 22 and to reverse bias diode 23 such that node 26 is charged to approximately the V.sub.O voltage. The charging current through diode 23, proportional to the integrated photon flux, is measured at the output circuit 20. When the pulse stops at the end of the pulse time, diodes 22 and 23 are both reverse biased, thus restoring the V.sub.O voltage at node 26. During the scan time the charges of the photo currents derived from the photo-generated carriers are stored in the reverse-biased junction capacitance of diode 23 and capacitors 22-23. As the photon-generated carriers are accumulated, the voltage at node 26 decays from the initially charged V.sub.O voltage. The voltage drop at node 26 is substantially directly proportional to the integral of the incident light during the scan time. Subsequently, on the following read out period, another pulse of V.sub.O voltage is applied to the anode of diode 22 to forward bias diode 22 which recharges node 26 to approximately the V.sub.O voltage. When the pulse ends, both diodes 22 and 23 are reverse biased and the above described photo detection process repeats.
Disadvantages are, however, associated with the above described prior art pixel structure. One disadvantage associated is that the switching diode typically experiences a non-linear forward bias characteristic during its forward bias operation. This is due to the fact that when the voltage at node 26 approaches the V.sub.O voltage of the pulse during the pulse time, the voltage across the switching diode approaches zero. This results in a very small forward bias voltage on the switching diode. The very small forward bias voltage on the switching diode typically causes the switching diode to operate in its non-linear forward bias region with very high impedance. As a result, the time constant formed by the non-linear forward bias impedance of the switching diode and the accumulated parasitic capacitance at node 26 typically exceeds the width of the pulse applied at the switching diode, thus causing node 26 not to be fully charged during the pulse time. This typically results in the incident light not being accurately measured. If the width of the pulse is extended to accommodate the time constant, the pixel read out rate will reduce to a point where array cannot be used in many applications.
Another form of prior art uses a thin film transistor ("TFT") as the switch to read out and isolate the pixel. The process required to fabricate a TFT is much more complicated, hence affecting the yield.